Analogue-to-digital converters are an important component in many electrical sensor, control and communications systems.
Currently there are two basic types of analogue-to-digital converters (ADC). Analogue-to-digital converters with an open loop and fed-back analogue-to-digital converters. An analogue-to-digital converter with an open loop generates a digital code directly from an analogue input signal and is generally asynchronous in terms of operation. In contrast, a fed-back analogue-to-digital converter (DAC=Digital-to-Analogue Converter) generates a digital code from an analogue input signal, converts this digital code back into an analogue signal and uses this analogue signal as a feedback signal.
An example of fed-back converters are sigma-delta analogue-to-digital converters. Sigma-delta analogue-to-digital converters achieve high resolution by means of a high clock frequency instead of precisely matching circuit-internal components such as, for example, resistors and capacitors which are used in analogue-to-digital converters with an open loop. Sigma-delta analogue-to-digital converters are therefore used in many integrated circuits.
A sigma-delta analogue-to-digital converter receives an analogue input signal and subtracts a feedback signal from the input signal in order to generate an analogue fault signal. The fault signal is processed by a low-pass filter and then quantized in a quantizer in order to generate a digital output signal. A digital-to-analogue converter with feedback converts the digital output signal into an analogue signal or the feedback signal. The quantizer usually has a voltage divider for generating reference voltages and a respective comparator for each reference voltage. Each comparator compares the analogue input signal with a respective reference voltage (quantization stage) and forms the digital output signal from the comparison results. The sigma-delta analogue-to-digital converter is operated with a clock frequency or sampling frequency fs which according to the Nyquist criterion is at least twice as high as the highest frequency components of the analogue input signal. The ratio of the sampling frequency fs which is actually used to the minimum necessary sampling frequency is referred to as the oversampling ratio.
In sigma-delta analogue-to-digital converters, non-linearity reduces the signal-to-noise ratio in a useful frequency range, generates harmonics in the output spectrum of the output signal and changes the noise in the frequency range fs/20 to fs/2. The non-linearity is caused by the quantization steps of the quantizer, by offset errors or offset voltages Vos at the inputs of the comparators of the quantizer and by mismatchings of elements of the non-ideal voltage divider such as, for example, resistors and elements of the digital-to-analogue converter with feedback, for example power sources. The offset voltages Vos at the inputs of the comparators are dominated by process-internal threshold voltage mismatchings and become increasingly problematic as the signal excursion is reduced or the quantization increment is reduced.
The signal-to-noise ratio (SNR) and the resolution of the sigma-delta analogue-to-digital converter can be improved by increasing the sampling frequency or the oversampling ratio. Quantization noise of the quantizer is thus distributed over a larger frequency range and the useful frequency range and can be sufficiently damped or removed outside the useful frequency range downstream of the quantizer using a conventional filter.
A known possible way of solving the problem of offset voltages is to correct the offset voltages at the inputs of the comparators in the sigma-delta analogue-to-digital converter using a calibration algorithm. Disadvantages of this method are that it is costly and that there must be sufficient time available for the calibration before the sigma-delta analogue-to-digital converter is switched on.
A known possible way of solving the problem of mismatchings of resistance is to improve the matching of the components in the quantizer. However, a disadvantage of this solution is that the parasitic influences and the use of surface area increase quadratically with the improvement in the matching.
U.S. Pat. No. 6,346,898 B1 describes a further possible way of solving the abovementioned problems.
FIG. 2 shows a known sigma-delta analogue-to-digital converter which is described in U.S. Pat. No. 6,346,898 B1 and is shown there in FIG. 2. The sigma-delta analogue-to-digital converter 200 has a summing element 202, a noise-forming filter 204, a quantizer 206, a digital filter 208, a control device for dynamic element matching (DEM) 210, a switching device 212 and a digital-to-analogue converter 214. One input of the sigma-delta analogue-to-digital converter 200 is connected to a first input of the summing element 202. A second input of the summing element 202 is connected to an output of the digital-to-analogue converter 214. One output of the summing element 202 is connected to an input of the noise-forming filter 204. One output of the noise-forming filter 204 is connected to an input of the quantizer 206. One output of the quantizer 206 is connected to an input of the digital filter 208 and to an input of the control device for dynamic element matching 210. One output of the control device for the dynamic element matching 210 is connected to an input of the switching device 212. One output of the switching device 212 is connected to an input of the digital-to-analogue converter 214. The control device for the dynamic element matching 210, the switching device 212 and the digital-to-analogue converter 214 form a feedback loop to the summing element 202. The noise-forming filter 204 is normally a low-pass filter. The quantizer 206 typically has an array of comparators. The digital filter 208 is decimation filter.
An analogue output signal 216 of the digital-to-analogue converter 214 is combined with an analogue input signal 218 of the sigma-delta analogue-to-digital converter 200 by the summing element 202 in order to generate an analogue fault signal 220. The fault signal 220 is filtered by the noise-forming filter 204 in order to generate a filtered output signal 222 which is fed to the quantizer 206. A digital multibit output signal 224 of the quantizer 206 is an input signal of the digital filter 208 and of the control device for the dynamic element matching 210. The digital filter 208 divides the useful frequency range from the multibit output signal 224 and passes on said range for digital signal processing as an output signal 226 of the sigma-delta analogue-to-digital converter 200. The control device for the dynamic element matching 210 and the switching device 212 determine the use of the elements in the digital-to-analogue converter 214. The control device for the dynamic element matching 210 may, for example, be designed to ensure that all the elements of the digital-to-analogue converter 214 are used in a proportionally identical fashion with respect to time.
FIG. 3 shows a further known sigma-delta analogue-to-digital converter which is described in U.S. Pat. No. 6,346,898 B1 and shown there in FIG. 4. The sigma-delta analogue-to-digital converter 300 has a summing element 302, a noise-forming filter 304, a quantizer 328 with a control device for dynamic element matching (DEM), a digital filter 308 and a digital-to-analogue converter 314. One input of the sigma-delta analogue-to-digital converter 300 is connected to a first input of the summing element 302. A second input of the summing element 302 is connected to an output of the digital-to-analogue converter 314. One output of the summing element 302 is connected to an input of the noise-forming filter 304. One output of the noise-forming filter 304 is connected to an input of the quantizer 328. One output of the quantizer 328 is connected to an input of the digital filter 308 and to an input of the digital-to-analogue converter 314. The noise-forming filter 304 is generally a cascade of integrators. The quantizer 328 has comparators. The digital filter 308 generally has a decimator which outputs the output signal 326 with a suitable sampling rate for the system. The digital filter 308 is, for example, a low-pass filter.
An analogue input signal 318 of the sigma-delta analogue-to-digital converter 300 is added to a feedback signal or an analogue output signal 316 by the digital-to-analogue converter 314 in order to generate a fault signal 320 which is fed to the noise-forming filter 304. A filtered output signal 322 of the noise-forming filter 304 is fed to the quantizer 328 which generates a digital multibit output signal 324. The quantizer 328 uses the comparators to select that multibit output signal 324 which is closest to the filtered output signal 322 of the noise-forming filter 304. The control device for the dynamic element matching (DEM) in the quantizer 328 determines the use of the comparators. The digital multibit output signal 324 is fed to the digital filter 308 and is filtered by it in order to remove the quantization noise which lies outside the useful frequency range and is caused by the quantizer 328, and in order to generate a digital output signal 326 for further digital signal processing. The output signal 326 is the output signal of the sigma-delta analogue-to-digital converter 300. The multibit output signal 324 is also fed to the digital-to-analogue converter 314 which converts the multibit output signal 324 into the analogue output signal 316. It is to be noted that the ratio between the sampling rate of the noise-forming filter 304 and the output sampling rate of the output signal 326 is the oversampling ratio.
FIG. 4 shows the quantizer from FIG. 3 which is described in U.S. Pat. No. 6,346,898 B1 and is shown there in FIG. 5. The quantizer 328 has a series of resistors 330, a switching device 332, a control device for dynamic element matching 334 and a series of comparators 336. The switching device 332 contains switches 338 which connect a respective input of said switching device 332 to a selected output 340 of same.
The filtered output signal 322 from the noise-forming filter 304 (FIG. 3) is fed to the series of comparators 336. The other signals to the comparators 336 are generated by the series of resistors 330 which divides the voltage V+/V− into reference voltages 342. These reference voltages 342 are typically spaced apart at equal intervals. The comparators 336 generate the multibit output signal 324. The dynamic element matching is carried out by the switching device 332 which is controlled by the control device for the dynamic element matching (DEM) 334 by means of control signals 344. The switches 338 are switched by these control signals 344 on the basis of the multibit output signal 324. Only one configuration of the switching device 332 is shown for the sake of clarification. However, any reference voltage 342 can be connected to any output 340 by means of a switch 338 under the control of the control signals 344. It is to be noted that each reference voltage 342 is fed to just one comparator 336.
While the control device is operating for the dynamic element matching 210 and 334 in FIGS. 2 and 4, the most necessary elements m are determined from a total number of n elements of the digital-to-analogue converter 214 or of the quantizer 328, with the most necessary elements then being used. The degree of need is updated for the next selection on the basis of the use over time. In the case of dynamic 1st order element matching the degree of need is based on the total use of each element, with the most necessary element being the element which has been used least. In the case of dynamic 2nd order element matching the timed control of the use is also taken into account.
The linearity error in the quantizer 328 is, as mentioned, determined inter alia by the offset voltages at the inputs of the comparators at the decision threshold. On the other hand, the linearity error in the digital-to-analogue converter 214 is determined by the mismatching of all the active elements of the said digital-to-analogue converter 214. Since only one comparator, specifically the comparator whose reference voltage is still just below the voltage to be digitized ever determines the linearity in the quantizer 328, and a plurality of elements determine the linearity in the digital-to-analogue converter 214, the known DEM method described above has different effects in the digital-to-analogue converter and in the quantizer.
One disadvantage of the devices and methods described in U.S. Pat. No. 6,346,898 B1 is that the second and third harmonics of the output signal of the sigma-delta analogue-to-digital converter are only slightly damped. The output spectrum of the output signal also exhibits an increase at measurements in the region fs/20 to fs/2.
The article A Dynamic Element Matching Technique for Reduced-Distortion Multibit Quantization in sigma-delta-ADCs IEEE Transaction on Circuits and Systems-II: Analogue and Digital Signal Processing, VOL. 48, NO. 2, FEBRUARY 2001, by Eric Fogleman and Ian Galton describes a further known possible way of solving the problem of offset voltages at the inputs of the comparators.
In Fogleman et al., the interference which is introduced at the inputs of the comparators by the offset voltages is reduced by modulating the sign of each offset voltage Vos with a random bit sequence. This method is referred to as comparator offset DEM in Fogleman et al.
FIG. 5 shows a known comparator which is described in the article by Eric Fogleman and Ian Galton and is shown there in FIG. 3. The comparator offset DEM is implemented in a sigma-delta analogue-to-digital converter using swapper cells S1 and S2 at an analogue input and an analogue output of each comparator k. In FIG. 5, Vin[n] is the instantaneous value of an analogue input signal, refk is a reference level of a voltage divider connected upstream, r[n] is a control signal and yk[n] is a digital output signal sequence. The control signal r[n] is a ±pseudo-random 1-bit sequence. If r[n]=1, the direct paths through S and S2 are selected, and if r[n]=−1 the swapped paths through S1 and S2 are selected. The swapping causes two quantization thresholds per comparator, which are selected by the value of the pseudo-random sequence r[n].
A disadvantage of the method by Eric Fogleman and Ian Galton is that as a result only the even numbered harmonics such as the second, fourth and sixth harmonic in the output signal of the sigma-delta analogue-to-digital converter can be reduced. The uneven harmonics such as the third, fifth and seventh harmonic are not reduced.